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Logic Minimization Algorithms For Vlsi Synthesis Essay

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Graduate Course Information


ECE 574A - Computer-Aided Logic Design

Credits: 3.00

Course Website:

UA Catalog Description:

Course Assessment:

Exam: 4 (lowest score dropped)

Project:  4 programming projects

Participation:  12-15 participation activities (1 dropped)

Grading Policy:

Typically: 55% Exams (4, lowest score dropped),

                40% Programming Assignments,

                  5% Participation/In-Class Exercises.

Course Summary:

This course is an introduction to Computer-Aided Logic Design. This is a highly active research area, enabling the design of increasingly complex digital systems. In this course we will mainly focus on three areas - specification, synthesis, and optimization. We will look at how to specify functionality at a variety of abstractions, use industry-standard tools to simulate these designs, investigate some of the underlying optimization techniques utilized, as well as develop your own tools. Topics include, but are not limited to (1) Register-Transfer Level (RTL) Design, (2) Behavioral Synthesis, (3) Optimization and Tradeoffs of Combinational and Sequential Circuits, (4) Exact and Heuristic Minimization of Two-Level Circuits.

Students will be expected to implement a variety of Verilog and C/C++ projects throughout the semester. While specific programming assignments may change with the course offering, projects typically focus on the implementation of optimization and synthesis methods discussed in class, as well as the RTL design.